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# Logic Gates

Logic gates are the building blocks of a digital circuit.

Every terminal in a logic gate will always be in one of the two binary states (0) or (1).

These binary states represent the presence (1), or absence (0), of an electrical voltage. Binary (1) can be referred to as positive or ON, whilst binary (0) can be called negative or OFF.

There are many types of logic gates, each with their own characteristics.

## The Logic Gates

Name | Symbol | Explanation | Notation |
---|---|---|---|

NOT |
Inverses the current output, therefore positive (1 or ON) becomes negative (0 or OFF), whilst negative (0 or OFF) would become positive (1 or ON). | Z = NOT A | |

AND |
Both inputs have to be positive (1) before the output is also positive (1). | Z = A AND B | |

OR |
At least one input has to be positive (1) to give a positive output (1 or ON). Both inputs could also be positive. | Z = A OR B | |

NAND |
NOT AND. The same as AND, but then inverse (NOT) the outcome. So, perform AND first, then apply a NOT to the output. | Z = A NAND B | |

NOR |
NOT OR. The same as OR, but then inverse (NOT) the outcome. So, perform OR first, then apply a NOT to the output. | Z = A NOR B | |

XOR |
Exclusive OR. Only one input is allowed to be positive (1 or ON) to give a positive output (1). If both inputs are positive (1) then there is a negative outcome (0, or OFF). | Z = A XOR B |

## Logic Gate Truth Tables

Truth tables are used to calculate the output from a logic gate or circuit.

Every possible binary input combination is covered in a truth table. From this, we can clearly see what the output would be in any scenario.

## NOT

Input A | Output Z |
---|---|

1 | 0 |

0 | 1 |

## AND

Input A | Input B | Output Z |
---|---|---|

0 | 0 | 0 |

0 | 1 | 0 |

1 | 0 | 0 |

1 | 1 | 1 |

## OR

Input A | Input B | Output Z |
---|---|---|

0 | 0 | 0 |

0 | 1 | 1 |

1 | 0 | 1 |

1 | 1 | 1 |

## NAND

Input A | Input B | Output Z |
---|---|---|

0 | 0 | 1 |

0 | 1 | 1 |

1 | 0 | 1 |

1 | 1 | 0 |

## NOR

Input A | Input B | Output Z |
---|---|---|

0 | 0 | 1 |

0 | 1 | 0 |

1 | 0 | 0 |

1 | 1 | 0 |

## XOR

Input A | Input B | Output Z |
---|---|---|

0 | 0 | 0 |

0 | 1 | 1 |

1 | 0 | 1 |

1 | 1 | 0 |